Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a fuse circuit which stores, for example, an address corresponding to a defective area of the memory device.
In general, a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRAM) is provided with a large number of memory cells. As fabrication technologies have developed, the integration density of the semiconductor memory device gradually increases and the number of memory cells also gradually increases. When a fail occurs in an area of the memory device, for example, one of the memory cells, a corresponding semiconductor memory device may not perform a desired operation and thus may be discarded as a defective product.
As fabrication technologies for semiconductor memory devices have further developed, only a few memory cells may become defective. Here, if an entire semiconductor memory device is discarded as a defective product, the yield of products may suffer. Therefore, a redundancy memory cell may be provided within a semiconductor memory device. When a defect occurs in a normal memory cell, the defective memory cell may be replaced with the redundancy memory cell.
Meanwhile, a semiconductor memory device includes a fuse circuit which can store, for example, repair information. Methods for storing a fuse include an electrical cutting method and a laser cutting method. According to the electrical cutting method, a target fuse to be cut is melted and cut by applying an over-current to the target fuse. According to the laser cutting method, a target fuse to be cut is blown by a laser beam. In general, since the laser cutting method is simpler than the electrical cutting method, the former is widely used.
As described above, the address corresponding to the memory cell to be replaced may be stored in the fuse circuit, and the semiconductor memory device may be repaired by the fuse circuit.
FIG. 1 is a circuit diagram illustrating a fuse circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the fuse circuit according to an example includes storage units 110, a precharge unit 120, and an output unit 130.
The plurality of storage units 110 may include a plurality of fuses for storing addresses corresponding to memory cells to be replaced, and output information of the replacement stored in the fuses to a first node N_B in response to a plurality of selection signals XMAT<0:N> (where N is a natural number). The plurality of selection signals XMAT<0:N> may be signals corresponding to a region activated among a plurality of memory cell arrays in response to an active command and an address. The plurality of selection signals XMAT<0:N> may be inputted to corresponding transistors.
For convenience, a storage unit 111 among the storage units 110 will be described below.
The storage unit 111 may include a fuse F and an NMOS transistor NM coupled between a second node N_C and a ground voltage (VSS) terminal. The NMOS transistor NM is configured to be turned on/off in response to a zeroth selection signal XMAT<0> which is one of the plurality of selection signals XMAT<0:N>. When the NMOS transistor NM is turned on, the voltage levels of the first and second nodes N_B and N_C may be determined according to whether the fuse F is cut or not. A detailed description thereof will be provided later with reference to FIG. 2.
Meanwhile, the precharge unit 120 is configured to precharge the first node N_B to a power supply voltage VDD in response to a precharge signal WLCB. The output unit 130 is configured to output information, for example, a repair information, and an information output RADD may have a logic level corresponding to the voltage level of the output node N_A.
FIG. 2 is a waveform diagram explaining the operation of the fuse circuit of FIG. 1. For convenience, the storage unit 111 among the plurality of storage units 110 will be described representatively.
Referring to FIGS. 1 and 2, the first node N_B may be precharged to the power supply voltage VDD in response to the precharge signal WLCB which maintains a logic low level prior to an active operation. At this time, the voltage level of the second node N_C between the fuse F and the NMOS transistor NM may be determined according to whether the fuse F is cut or not. That is, if the fuse F is not cut, the second node N_C may have the same voltage level as that of the first node N_B. If the fuse F is cut, the second node N_C becomes a floating state.
After the active operation, when the precharge signal WLCB changes from a logic low level to a logic high level and the zeroth selection signal XMAT<0> changes from a logic low level to a logic high level, the voltage levels of the first and second nodes N_B and N_C may be determined according to whether the fuse F is cut or not. That is, if the fuse F is not cut, the first node N_B may become a logic low state corresponding to the ground voltage VSS, and the second node N_C may have the same voltage level as that of the first node N_B. If the fuse F is cut, the first node N_B may become a logic high state corresponding to the power supply voltage VDD, and the second node N_B may become a logic low state corresponding to the ground voltage VSS. The repair information output RADD becomes a logic high state if the fuse F is cut, and becomes a logic low state if the fuse F is not cut.
Meanwhile, as fabrication technologies for semiconductor memory devices advance, the size of the fuse becomes smaller and a cut region of the fuse becomes smaller. The reduction in the cut region of the fuse means that a fuse may easily change to an uncut state for various reasons. For example, such change may be caused by an electric field generated by a voltage difference between both terminals of a cut fuse. Consequently, the cut fuse may operate as an uncut fuse and a circuit including such a fuse may malfunction.
A case in which a fail occurs in a fuse will be described in more detail with reference to FIGS. 1 and 2. For convenience, a case in which the fuse F is cut will be described below.
If the fuse F of FIG. 1 is cut, the first node N_B and the second node N_C may have different voltage levels as illustrated in FIG. 2. That is, if the zeroth selection signal XMAT<0> is at a logic high level, the first node N_B may become a logic high state corresponding to the power supply voltage VDD, and the second node N_C may become a logic low state corresponding to the ground voltage VSS. In this case, a voltage difference may be maintained between both terminals of the fuse F. Thus, reconnection of the cut fuse may occur. Consequently, even though the fuse F is cut, the fuse F may become an uncut state due to the voltage difference between both terminals of the fuse F and thus the fuse fail may occur.